1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Prior Art
In a semiconductor memory such as a RAM (random access memory), so-called redundant memory cell construction is adopted which comprises a built-in defective bit relief circuit. According to this construction, some redundant memory cells in which redundant bits are stored are arranged beforehand in a memory device and defective memory cells containing defective bits are replaced by the above redundant memory cells containing redundant bits to improve the percent production yield of operable memory devices.
However, because a chip area increased by arranging for additional memory cells having such redundant bits, it is inappropriate to provide for a substantial number of additional memory cells having redundant bits as built-in the memory chip from the viewpoint of maintaining miniaturization of the chip and economy. Hence, heretofore, additional memory cells having only 2-4 redundant bits are generally provided in rows and columns of a memory device. Memory devices having more than 2-4 defective memory cells providing defective bits are scrapped as defective goods under present commercial practices.